1. Field of the Invention
The present invention relates to digital logic devices. More specifically, the present invention relates to techniques and mechanisms for testing arbitration and bus-mastering logic associated with digital logic devices. Furthermore, the present invention relates to random modulation of response times to improve system performance in a system containing arbitration logic.
2. Description of Related Art
Conventional programmable chip systems generally include a variety of primary and secondary components, such as processors, memory, parallel input/output interfaces, timers, etc. In some cases, the primary and secondary components can interact in a variety of ways. Arbitration logic is used to manage interactions between primary and secondary components. In systems with relatively complex secondary component configurations, arbitration logic can also become complex.
However, techniques and mechanisms for testing arbitration logic associated with programmable chip systems are limited.
Consequently, it is therefore desirable to provide improved methods and apparatus for testing programmable chip systems and particularly arbitration logic in an efficient manner by allowing the simulation of a variety of interaction sequences.